Logic simulation apparatus and circuit simulation apparatus

Details Logic simulation apparatus and circuit simulation apparatus Logic simulation apparatus and circuit simulation apparatus

1993-09-14

1995-11-28

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054714095

ABSTRACT:
There are provided a logic simulator apparatus and a circuit simulation apparatus capable of simulation based on signal propagation delay time with high reliability. A voltage drop calculating portion (9) calculates a voltage drop value (Vi) on the basis of power-supply information (D4), drain current (Ii) and voltage drop resistance (Ri). A propagation delay calculating portion (10) calculates delay time (Di) required for each element to propagate a logic signal value on the basis of gain coefficient (.beta.i), interconnection parasitic capacitance (Cj) and voltage drop value (Vi). A logic simulation performing portion (12) performs the logic simulation on the basis of the circuit connection data (D22) provided with the delay time (Di). Accordingly, logic and circuit simulation can be accomplished on the basis of the signal propagation delay time with high reliability.

REFERENCES:
patent: 5047971 (1991-09-01), Horwitz
patent: 5202841 (1993-04-01), Tani
patent: 5278769 (1994-01-01), Bair et al.
patent: 5305229 (1994-04-01), Dhar
patent: 5349539 (1994-09-01), Moriyasu
patent: 5359534 (1994-10-01), Fujiki et al.
patent: 5379232 (1995-01-01), Konoda
"Automated Extraction of SPICE Circuit Models from Symbolic Gate Matrix Layout with Printing" by Freeman et al., IEEE 23rd Design Automation Conference, 1986, pp. 418-424.
"Resistance Extraction in a Hieriarchical IC Artwork Verification System" by Mori et al., IEEE 1985, pp. 196-198.
"Excl: A Circuit Extractor for IC Designs" by S. P. McCormick, IEEE 21st Design Automation Conference, 1984, pp. 616-623.
"Principles of CMOS VLSI Design-A System Perspective", pp. 39-41; 124-125, N. H. E. Weste, et al., Addison-Wesley Publishing Company, 1985.

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