Logic signal selection circuit

Details Logic signal selection circuit Logic signal selection circuit

1997-09-02

2000-02-15

Tokar, Michael

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

327355, 327298, 326104, H03K 1762

Patent

active

060257474

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a logic signal selection circuit for selecting a high frequency logic signal and outputting the selected logic signal with high timing resolution.


BACKGROUND ART

Because of the increasing operation speed in electric circuits, higher timing resolution is required in electric signals used in such electric apparatuses. In particular, a logic signal selection circuit which selectively outputs a logic signal out of many logic signals is required to have a high timing resolution.
FIG. 7 shows an example of a logic signal selection circuit generally used in the conventional technology. In this example, the number of input signals, which are negative logic, to an OR circuit is equal to the number of input signals n to a NAND circuit.
FIG. 8(a) shows an example in which an OR circuit having n negative logic inputs is formed of a CMOS circuit. In this circuit example, n gates which are N-channel MOS-FETs are connected in series while n gates which are P-channel MOSFETs are connected in parallel. As a consequence, a rising edge of an output signal waveform goes to a high level with a relatively short transition time, since one P-channel MOSFET drives wiring capacitance of the circuit and gate capacitance of the next stage. However, a falling edge of the output signal waveform requires a considerably long time for going down to a low level as shown in FIG. 8(b), since n stages of the N-channel MOSFETs drive the wiring capacitance and the gate capacitance of the next stage. This is because the overall ON resistance is large by the series connection of the n MOSFETs.
FIG. 9 shows an example of a logic signal selection circuit using transfer gates. In this example, one transfer gate, which is ON, drives through its ON resistance R, capacitance C of other n-1 transfer gates which are OFF. Therefore, rising and falling waveforms at a wired OR of the outputs of the transfer gates are affected by the capacitance C and the resistance R. Thus, it is not proper to use this circuit examples as a signal selection circuit for high repetition frequency signals.
As in the foregoing, in the conventional logic signal selection circuit, high frequency signal selection is not attainable, since the wiring capacitance, the gate capacitance of the next stage and the capacitance of the transfer gates which are in the OFF state have to be charged by means of voltage changes.
Therefore, it is an object of the present invention to provide a logic signal selection circuit which is capable of selecting a high frequency logic signal with high timing resolution.


DISCLOSURE OF THE INVENTION

The structure of a logic signal selection circuit of the present invention includes a current input type sense amplifier 320 which is provided with a threshold value which is an output of an equivalent center current generator 310 and positive logic input signals through transfer gates, a current input type sense amplifier 321 which is provided with a threshold value which is an output of an equivalent center current generator 311 and negative logic input signals through transfer gates, a differential amplifier 340 which receives and amplifies an output of the current input type sense amplifier 320 whose delay times are fine adjusted by a delay time adjuster 330, a differential amplifier 341 which receives and amplifies an output of the current input type sense amplifier 321 whose delay times are fine adjusted by a delay time adjuster 331, and a logic circuit 350 which receives both outputs of the differential amplifiers 340 and 341, and generates a logical sum of the both outputs.
Because there is no voltage change in the input of the current input type sense amplifier, current flows will not occur to the capacitance C of the transfer gates which are in the OFF state and are connected at the input of the current input type sense amplifier. Thus, it is able to output the selected input signal with high timing resolution and with high speed.
Further, by classifying the positive logic inputs and the negative logic i

REFERENCES:
patent: 4986666 (1991-01-01), Homma et al.

Affiliated with

Also associated with

Rating

Logic signal selection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic signal selection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic signal selection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1908776