Logic signal multiplier circuit

Details Logic signal multiplier circuit Logic signal multiplier circuit

1984-09-17

1987-04-07

Salce, Patrick R.

Electric power conversion systems

Current conversion

With voltage multiplication means

363 70, 320 1, 307110, H02M 725

Patent

active

046565744

ABSTRACT:
There is disclosed a logic signal multiplier circuit which includes the interconnection of a plurality of inverters having outputs interconnected by a capacitor. Each of the inverters includes complementary transistors having their gates connected to a common terminal such that each inverter may be controlled by a separate clock control signal. The control signals are coupled to provide a three-phase operation of the circuit which insures (1) charging of the capacitor between the outputs of the inverters during a first time period, (2) an increase of the voltage at a node of one of the inverters to a value which is twice the value of the supply voltage driving the inverters during a second time period, and (3) coupling of that same node to ground during a third time period. Diodes are interconnected in each of the inverter circuits to prevent discharge of the capacitor during times that selected ones of the transistors forming the inverter circuits are conductive.

REFERENCES:
patent: 3944908 (1976-03-01), Oki
patent: 4041522 (1977-08-01), Oguey et al.
patent: 4068295 (1978-01-01), Portmann
patent: 4259600 (1981-03-01), Fellrath et al.
patent: 4559483 (1985-12-01), Jundt et al.
E. Vittoz, "Microwatt Switched Capacitor Circuit Design", 1982, Electrocomponent Science and Technology, vol. 9, pp. 263-273.
"A CMOS Voltage Reference", By Tsividis, Ulmer, IEEE Journal of Solid State Circuits, vol. SC-13, No. 6, Dec. 1978.

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