Logic process DRAM

Details Logic process DRAM Logic process DRAM

2006-06-09

2009-10-27

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S072000, C365S051000, C365S189020, C365S230020

Reexamination Certificate

active

07609538

ABSTRACT:
A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line and a second bit line. The first bit line and the second bit line within each bit line pair are aligned adjacent to each other. Each of a plurality of word lines is associated with the bit lines such that an array is formed by the bit lines and the associated word lines. Each bit line is associated with both first and second interconnect layers. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.

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