Logic process DRAM

Details Logic process DRAM Logic process DRAM

2005-09-20

2005-09-20

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S149000, C257S288000, C257S300000, C257S068000, C257S071000, C257S908000

Reexamination Certificate

active

06947324

ABSTRACT:
A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

REFERENCES:
patent: 4914502 (1990-04-01), Lebowitz et al.
patent: 4959698 (1990-09-01), Shinichi
patent: 4967396 (1990-10-01), Kajigaya et al.
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5014110 (1991-05-01), Satoh
patent: 5241497 (1993-08-01), Komarek
patent: 5416734 (1995-05-01), Hidaka et al.
patent: 5534732 (1996-07-01), DeBrosse et al.
patent: 5579256 (1996-11-01), Kajigaya et al.
patent: 5618747 (1997-04-01), Lou
patent: 5625234 (1997-04-01), Suzuki et al.
patent: 5650647 (1997-07-01), Taguchi et al.
patent: 5671175 (1997-09-01), Liu et al.
patent: 5808334 (1998-09-01), Taguchi
patent: 5864181 (1999-01-01), Keeth
patent: 5870343 (1999-02-01), Chi et al.
patent: 5892702 (1999-04-01), Okamoto et al.
patent: 5917744 (1999-06-01), Kirihata et al.
patent: 6008084 (1999-12-01), Sung
patent: 6008514 (1999-12-01), Wu
patent: 6034879 (2000-03-01), Min et al.
patent: 6084307 (2000-07-01), Keeth
patent: 6165833 (2000-12-01), Parekh et al.
patent: 6168985 (2001-01-01), Asano et al.
patent: 6172389 (2001-01-01), Sakoh
patent: 6205044 (2001-03-01), Feurle et al.
patent: 6222275 (2001-04-01), Keeth
patent: 6258663 (2001-07-01), Koh et al.
patent: 6342419 (2002-01-01), Tu
patent: 6462998 (2002-10-01), Proebsting
patent: 6570781 (2003-05-01), Lee et al.
patent: 6593183 (2003-07-01), Parekh et al.
patent: 2002/0140020 (2002-10-01), Wu et al.
patent: 404298073 (1992-10-01), None
patent: 06029487 (1994-02-01), None
patent: 9300811 (1993-02-01), None

Affiliated with

Also associated with

Rating

Logic process DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic process DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic process DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3438461