Logic process DRAM

Details Logic process DRAM Logic process DRAM

2003-01-02

2004-01-20

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S185010, C365S185050, C365S185020, C438S254000, C438S253000

Reexamination Certificate

active

06680859

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) device, and more particularly to an apparatus and a method for improving signal-to-noise ratio and reducing overall bit line capacitance and area in a DRAM.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices include an array of individual memory cells for storing information. These memory cells are dynamic in that they will only hold a particular quantity of information for a short period of time. Therefore, the cells must be read and refreshed at periodic intervals. A common conventional cell configuration includes one transistor and one capacitor. The transistor is connected between a bit line and the capacitor. The transistor is gated by a word line signal. A bit of information is read from the cell to the associated bit line or written to the cell from the bit line through the transistor.
DRAM devices are very well known in the literature and are the subject of many patents. For example, see U.S. Pat. Nos. 6,222,275; 6,205,044; 6,168,985; 6,084,307; 6,034,879; 6,008,084; 5,870,343; 5,864,181; 5,671,175; 5,625,234; 5,579,256; 5,534,732; 5,416,734; 5,241,497; 5,014,110; 4,970,564; 4,967,396; 4,914,502; and KR9300811, the contents of each of which are incorporated herein by reference.
Referring to
FIG. 1
, a top view of a traditional folded bit line DRAM cell arrangement
100
includes three bit line pairs
105
,
110
,
115
and six word lines
120
,
125
,
130
,
135
,
140
,
145
, with memory cells
150
located at every other bit line—word line intersection. In a folded bit line architecture, along each word line direction, there is a cell connected to every other bit line. Within each bit line pair, the bit line with the cell is called the sense bit line, and the adjacent bit line without a cell is called the reference bit line. The sense bit line and adjacent reference bit line are respectively coupled to the positive and negative inputs of a differential amplifier
155
. In a typical scenario, prior to activation of word line w
0
120
, all bit lines are precharged to a voltage level V
ref
. Cell A
160
and cell B
165
may be assumed to have an initial voltage of V
ref
+&Dgr;V. After w
0
is activated, both b
0
and b
1
will attain a value greater than V
ref
; this may be designated as V
ref
+&Dgr;V
x
. If b
0
remains at V
ref
, the voltage across the differential amplifier coupled to b
0
and b
0
would be V
ref
+&Dgr;V
x
−V
ref
=&Dgr;V
x
. However, because of the capacitances C
A
170
and C
B
175
; b
0
will not remain at V
ref
; rather, it will be V
ref
+&Dgr;V
n
, due to coupling from b
0
and b
1
. Hence, the differential voltage to the amplifier will be (V
ref
+&Dgr;V
x
)−(V
ref
+&Dgr;V
n
)=&Dgr;V
x
−&Dgr;V
n
. Thus, the differential voltage is reduced as a result of the effect of the capacitances C
A
and C
B
.
Referring to
FIG. 2
, a cross-sectional view of the arrangement
100
illustrates the cross-coupling capacitances
205
between adjacent bit lines. Each bit line pair is connected to a substrate
210
via a diffusion region
215
. As the number of cells in a DRAM increases, each bit line is connected to more cells, and bit line capacitance increases. As technology progresses toward DRAMs having larger information capacities, bit line capacitance of conventional designs becomes unacceptably high. Accordingly, there is a need for DRAM cell arrays having reduced bit line capacitance.
Referring to
FIG. 9
, a physical construction of the arrangement
100
is illustrated. A gate
905
of a transistor is connected to a substrate
910
by a gate oxide
915
. A cell plate
920
is located in horizontal alignment with the gate
905
, but with some minimum lateral spacing S. A bit line contact
925
connects a bit line to the a source of the transistor. A diffusion layer
930
is a drain of the transistor. As the number of cells in a DRAM increases, the cumulative effect of the minimum lateral spacings between transistor gates and cell plates causes the area of the DRAM to become unacceptably high. Accordingly, there is a need for a DRAM cell array having reduced overall area.
SUMMARY OF THE INVENTION
The present invention is intended to address the need for a DRAM device having a reduced bit line capacitance and reduced area.
In one aspect, the invention provides a semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit. The DRAM unit includes a substrate, a plurality of bit line pairs, a plurality of activatable word lines, a plurality of memory cells, a plurality of multiplexers, and a first interconnect layer and a second interconnect layer. Each bit line pair includes a first bit line and a second bit line. At most one word line can be activated at a time. Each bit line pair is associated with both interconnect layers. The first bit line and the second bit line within each bit line pair may be aligned with each other in an end-to-end arrangement. Each word line may be associated with either all of the first bit lines or all of the second bit lines, such that a first array is formed by the first bit lines and their associated word lines and a second array is formed by the second bit lines and their associated word lines. When a word line is activated, the array to which the activated word line belongs may act as a sense array, and the array to which the activated word line does not belong may act as a reference array. The device may also include an activatable dummy word line in the first array and an activatable dummy word line in the second array, and the device may then be configured to detect signal levels in a common mode.
The two interconnect layers may be metal layers, polysilicon layers, or one metal layer and one polysilicon layer. The first bit line and the second bit line within each bit line pair may be adjacent to each other. The first bit line and the second bit line within each bit line pair may be twisted at at least one point such that half of each bit line is associated with the first metal layer and half of each bit line is associated with the second metal layer. The first bit line and the second bit line within at least one bit line pair may be twisted at at least two points such that half of each bit line is associated with the first metal layer and half of each bit line is associated with the second metal layer. The DRAM unit may be manufactured using a logic process or a DRAM process.
In another aspect, a semiconductor integrated circuit device, including a dynamic random access memory (DRAM) unit, is provided. The DRAM unit includes a substrate, a plurality of bit line pairs, a plurality of activatable word lines, a plurality of memory cells, and a plurality of multiplexers. Each bit line pair includes a first bit line and a second bit line. At most one word line can be activated at a time. The first bit line and the second bit line within each bit line pair are aligned with each other in an end-to-end arrangement. Each word line is associated with either all of the first bit lines or all of the second bit lines, such that a first array is formed by the first bit lines and their associated word lines and a second array is formed by the second bit lines and their associated word lines. When a word line is activated, the array to which the activated word line belongs acts as a sense array, and the array to which the activated word line does not belong acts as a reference array. The device may also include an activatable dummy word line in the first array and an activatable dummy word line in the second array. The device may be configured to detect signal levels in a common mode by activating the dummy word line in the reference array and detecting the signal levels differentially as compared to the dummy. The DRAM unit may be manufactured using a logic process or a DRAM process.
In yet another aspect, the invention provides a semiconductor integrated circuit device, including a dyna

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