Logic performing cell for use in array structures

Details Logic performing cell for use in array structures Logic performing cell for use in array structures

1982-08-30

1985-02-19

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307481, 307577, 364716, 377 58, 377 61, H03K 19017, H03K 19096, H03K 1716, H03K 19177

Patent

active

045008000

ABSTRACT:
As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

REFERENCES:
patent: 4123669 (1978-10-01), Devine et al.
patent: 4130766 (1978-12-01), Patel et al.
patent: 4140921 (1979-02-01), Balasubramanian et al.
patent: 4183093 (1980-01-01), Kawagoe
patent: 4208728 (1980-06-01), Blahut et al.
patent: 4295064 (1981-10-01), Schuster
patent: 4393318 (1983-07-01), Takahashi et al.

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