Logic performance verification and transition fault detection

Details Logic performance verification and transition fault detection Logic performance verification and transition fault detection

1989-04-28

1991-05-21

Smith, Jerry

Excavating

G06F 1100

Patent

active

050181440

ABSTRACT:
In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.

REFERENCES:
patent: 4476431 (1984-10-01), Blum
patent: 4513418 (1985-04-01), Bardell
patent: 4698830 (1987-10-01), Barzilai
T. Lo, "LSSD Implemented with DCVS Logic", IBMTDB, vol. 26; No. 11, 4/1984, pp. 5805-5810.

Affiliated with

Also associated with

Rating

Logic performance verification and transition fault detection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic performance verification and transition fault detection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic performance verification and transition fault detection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-244438