Logic operation circuit having an exclusive-OR circuit

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307471, G06F 750, H03K 1921

Patent

active

047180358

ABSTRACT:
A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating a carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit. The sum signal selection circuit has first and second differential amplifiers respectively driven by first and second output signals which are inverted to each other and received from the exclusive-OR circuit so as to generate the sum signal in accordance with the carry input signal, and the carry input signal selection circuit has third and fourth differential amplifiers respectively driven in accordance with the first and second output signals from the exclusive-OR circuit so as to generate carry output signals in accordance with the first input signal and carry input signal, respectively.

REFERENCES:
patent: 3519810 (1970-07-01), Priel et al.
patent: 3590230 (1971-06-01), Nordquist
patent: 3612847 (1971-10-01), Jorgensen
patent: 4215418 (1980-07-01), Muramatsu
patent: 4408134 (1983-10-01), Allen
patent: 4547863 (1985-10-01), Colardelle
patent: 4564921 (1986-01-01), Suqanuma
patent: 4605871 (1986-08-01), Price et al.
patent: 4621338 (1986-11-01), Uhlenoff
patent: 4633104 (1986-12-01), Mallinson
Application of Digital Signal Processing; The Institute of Electronics and Communications Engineers of Japan.

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