Logic operation circuit and carry look ahead adder

Details Logic operation circuit and carry look ahead adder Logic operation circuit and carry look ahead adder

1997-02-26

1999-03-02

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

058779736

ABSTRACT:
An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 correspondint to the third and seventh bit of the input signals from a carry generation signal g7:0 and a carry propagation signal p7:0 generated by the both adders 2,12 and the carry c-1. The full adder of the second-stage 12 is constructed to add the 4 upper bits a7:4,b7:4 with setting a carry-in as 0 so as to generate a temporary summing signal sz7:4. A logical circuit 14 generates a true sum of 4 upper bits from a carry c3 to the third bit to the forth bit, a temporary sum sz7:4 and a carry propagation signal p7:4 generated by the full adder of the second-stage 12.

REFERENCES:
patent: 4761760 (1988-08-01), Tomoji
patent: 5117386 (1992-05-01), Persoon et al.
patent: 5357457 (1994-10-01), Terane
patent: 5544085 (1996-08-01), Sali
patent: 5701504 (1997-12-01), Timko
"Design of CMOS VLSI", published by Baifukan, 1989 (with English abstract).

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