Logic macro and protocol for reduced power consumption during id

Details Logic macro and protocol for reduced power consumption during id Logic macro and protocol for reduced power consumption during id

1992-09-04

1994-04-05

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072963, H03K 19173, H03K 301

Patent

active

053008316

ABSTRACT:
A control circuit and protocol are disclosed for an integrated circuit (such as a static PLA) wherein standby power is minimized during an idle processor state condition without loss of circuit outputs. For static PLAs, control circuits shutoff any active current path and drive the logic array outputs to zero whenever an idle state condition exists. Inputs to the logic array are held in static latches associated with the static PLA. The novel halt protocol includes: powering-down the logic macro upon initiation of an idle state by halting all internal clocks and then decoupling the logic array from power supply voltage VDD. Circuit power-up includes reactivating the logic array by first coupling the array to supply voltage VDD and allowing sufficient time for the outputs of the array and any associated logic to stabilize; and then restarting the previously halted internal clocks. Analogous techniques are also described for dynamic PLAs.

REFERENCES:
patent: 4233667 (1980-11-01), Devine et al.
patent: 4686386 (1987-08-01), Tadao
patent: 4697105 (1987-09-01), Moy
patent: 4760290 (1988-07-01), Martinez
patent: 4906862 (1990-03-01), Itano et al.
patent: 4906870 (1990-03-01), Gongwer
patent: 5008569 (1991-04-01), Roy
patent: 5187392 (1993-02-01), Allen
"Minimizing Power in High Performance", IBM Tecnical Disclosure Bulletin, vol. 32, No. 6B, pp. 362-367, 1989.
Cases et al. "CMOS Programmable Logic Array", IBM Technical Disclosure Bulletin, vol. 26, No. 11, pp. 5835-5837, 1984.

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