Logic level translator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307203, 307214, 307DIG1, H03K 114, H03K 1908

Patent

active

039744027

ABSTRACT:
A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

REFERENCES:
patent: 3766406 (1973-10-01), Bryant et al.

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