Logic level shifting circuit with minimal delay

Details Logic level shifting circuit with minimal delay Logic level shifting circuit with minimal delay

1990-09-04

1991-10-22

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 307446, 307355, 307495, 330253, H03K 19092, H03K 19094, H03K 1901, H03K 19003

Patent

active

050598295

ABSTRACT:
A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.

REFERENCES:
patent: 4829479 (1989-05-01), Mitsumoto et al.
patent: 4841175 (1989-06-01), DeMan et al.
patent: 4888501 (1989-12-01), Sanwo et al.
patent: 4916338 (1990-04-01), Metz

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