Logic level converting circuit

Details Logic level converting circuit Logic level converting circuit

1989-12-15

1991-02-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307264, H03K 19094, H03K 1920, H03K 190175, H03L 500

Patent

active

049926810

ABSTRACT:
A logic level converting circuit for converting an ECL level signal to a CMOS level signal comprises complementary signal generating means and level shifting means. The complementary signal generating means generates complementary signals in response to the ECL level input signal and a first reference voltage. The level shifting means operates as a flip-flop circuit, and includes a first and a second PMOS transistors which are either conductive or not conductive in response to the relationship between the complementary signals and a second reference voltage applied to the gate electrodes of the PMOS transistors.

REFERENCES:
patent: 4695744 (1987-09-01), Giordano
patent: 4697109 (1987-09-01), Honma et al.
patent: 4740718 (1988-04-01), Matsui
patent: 4813022 (1989-03-01), Matsui et al.
patent: 4815040 (1989-03-01), Matsui et al.
patent: 4845381 (1989-07-01), Cuevas
A 13ns/500 mW 64Kb ECL RAM, Katsumi Ogiue et al., ISSC Digest of Technical Papers, pp. 212-213, 1986.

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