Logic level converter circuit

Details Logic level converter circuit Logic level converter circuit

1992-02-26

1993-06-08

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307455, 307475, H03K 1901

Patent

active

052182444

ABSTRACT:
A logic level converter circuit for converting an ECL input signal to other type logic signal such as a TTL output signal comprises a differential comparator of an ECL type and an inverter which is formed by an output insulated-gate field-effect transistor and an output bipolar transistor connected in series between a higher potential power supply terminal and a lower potential power supply terminal. An output node of the differential comparator is directly connected to a gate of the output field-effect transistor and also coupled through a coupling capacitor to a base of the output bipolar transistor. An output of the differential comparator may be supplied to both the output transistors through an emitter follower circuit having a high driving capability. A bias voltage generating circuit may be provided for causing a DC bias current to flow in the output bipolar transistor. A change in the differential comparator output is immediately transmitted not only to the output field-effect transistor but also to the output bipolar transistor, so that it is possible to reduce the propagation delay time and to increase the operation speed of the circuit.

REFERENCES:
patent: 4999519 (1991-03-01), Kitsukawa et al.
patent: 5027013 (1991-06-01), Coy et al.
patent: 5073728 (1991-12-01), Ovens
patent: 5124581 (1992-06-01), Umeki
patent: 5146116 (1992-09-01), Sugimoto

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