Logic level control for impact ionization sensitive processes

Details Logic level control for impact ionization sensitive processes Logic level control for impact ionization sensitive processes

1990-11-19

1992-05-26

Laroche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307304, H03K 301

Patent

active

051171252

ABSTRACT:
A logic level control circuit prevents impact ionization in a CMOS integrated circuit. The substrate bias voltage of the CMOS integrated circuit is detected by the control circuit and a control signal is provided in response to the detected bias voltage. The bias voltage can be zero volts or negative five volts. If the bias voltage is zero volts, the control signal is a logic level one. If the bias voltage is negative five volts, the control signal is a logic level zero. The control signal is applied to the gate of at least one other controlled device on the integrated circuit for turning the controlled device on and off. The controlled device coupled to a further CMOS device and turning the controlled device on and off prevents impact ionization by allowing the controlled device to alternately divide a voltage level with the further CMOS device or be effectively removed from the circuit.

REFERENCES:
patent: 4705966 (1987-11-01), Van Zanlen
patent: 4820936 (1989-04-01), Veendrich et al.
patent: 5041739 (1991-08-01), Goto

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