Logic integrated circuit with a sequential circuit having edge t

Details Logic integrated circuit with a sequential circuit having edge t Logic integrated circuit with a sequential circuit having edge t

1992-11-19

1995-10-17

Ramirez, Ellis B.

Excavating

371 221, G01R 313177, G01R 31317

Patent

active

054597358

ABSTRACT:
A logic integrated circuit including a combinational logic circuit and 1 numbers of flip-flops for scanning, each flip-flop for scanning including first and second selectors and an edge trigger master/slave flip-flop having a data terminal and a clock terminal for inputting outputs of the first and second selectors and further having a mask terminal so as to operate an exact scan path by a small additional circuit. In a test mode, input signal terminals and output signal terminals of the flip-flops for scanning are connected in series via the first and second selectors controlled by a scan mode control signal and a test mode control signal output from a test signal generating circuit of an external testing device to constitute a sequential circuit for testing. An input signal for testing, output from the test signal generating circuit, is input to the input signal terminal of the first stage flip-flop for scanning is successively shifted upwards to the last stage flip-flop for scanning, and an output signal as a detection signal for discriminating is output from the output signal terminal of the last stage flip-flop for scanning to a waveform observing circuit of an external testing device.

REFERENCES:
patent: 4493077 (1985-01-01), Agrawai et al.
patent: 4701922 (1987-10-01), Kuboki et al.
patent: 4879718 (1989-11-01), Sanner
patent: 4894830 (1990-01-01), Kawai
patent: 4897838 (1990-01-01), Tateishi
patent: 5257267 (1993-10-01), Ishizaka
"Design for Testability--A Survey", Thomas W. Williams and Kenneth P. Parker, Proceedings of the IEEE, vol. 71, No. 1, Jan. 1983, pp. 98-112.

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