Logic having inhibit mean preventing erroneous operation circuit

Details Logic having inhibit mean preventing erroneous operation circuit Logic having inhibit mean preventing erroneous operation circuit

1980-07-30

1983-05-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307270, 307317R, H03K 326

Patent

active

043821979

ABSTRACT:
A logic circuit operable without erroneous operation is disclosed. The logic circuit comprises a first and a second switching transistor operating in response to the same signal, a first logic gate including an input transistor receiving a signal derived from the first switching transistor and a second logic gate receiving a signal derived from the second switching signal, in which the signal derived from the first switching transistor is independently fed to the first logic gate.

REFERENCES:
patent: 3191067 (1965-06-01), Zimmerman
patent: 3555294 (1971-01-01), Treadway
patent: 3806736 (1974-04-01), Wilhelm
patent: 4045690 (1977-08-01), Tam
patent: 4251742 (1981-02-01), Beelitz

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