Logic gates with controllable time delay

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307355, 307455, 307592, H03K 1923, H03K 522, H03K 1920

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active

051553880

ABSTRACT:
Apparatus for introduction of a controllable time delay in the transition of a logic device output signal from a first logical level to a second logical level, in response to change of an input signal, or the difference of two input signals from a third logical level to a fourth logical level, delivered to the logic device. In a first embodiment, a limiting amplifier receives an input signal S.sub.in and a threshold signal V.sub.T at its two terminals and forms an amplified difference output signal S.sub.out. A selected voltage level signal V.sub.L and S.sub.out are received at a signum function module and the output signal sgn(S.sub.out -V.sub.L) is formed and issued. The signum output signal is multiplied by a controllable real number m and is added to V.sub.L to form the threshold signal V.sub.T. The desired output signal S.sub.out makes a transition between the first and second logical levels, with a time delay that is controllable by choice of the number m. In a second embodiment, which also uses a signum function, two input signals, S.sub.in,1 and S.sub.in,2, give rise to two output signals, S.sub.out,1 and S.sub.out,2, and the difference signal S.sub.out,1 -S.sub.out,2 makes a transition between two logical levels with a time delay that depends controllably on choice of the number m.

REFERENCES:
patent: 4680480 (1987-07-01), Hopta
patent: 4714841 (1987-12-01), Shoji et al.
patent: 4737663 (1988-04-01), Varadarajan
patent: 4806791 (1989-02-01), Mizuide
patent: 4902916 (1990-02-01), Cecchi et al.
patent: 4928025 (1990-05-01), Kokado
patent: 5028815 (1991-07-01), Van De Plassche

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