Logic gate with controllable hysteresis and high frequency volta

Details Logic gate with controllable hysteresis and high frequency volta Logic gate with controllable hysteresis and high frequency volta

1994-05-10

1995-10-17

Grimm, Siegfried H.

Oscillators

Solid state active element oscillator

Transistors

327206, 331 17, 331 25, 331 34, 331 60, 331143, 331177R, H03K 303, H03K 3354, H03L 7099

Patent

active

054594375

ABSTRACT:
A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.5 nanosecond existing between the squarewave signals on the output terminals.

REFERENCES:
patent: 4301427 (1981-11-01), Suzuki et al.
patent: 4689581 (1987-08-01), Talbot
Low Skew CMOS PLL Clock Driver 100 MHz Version, MC88915T, Motorola Semiconductor Technical Data, pp. 67-77.

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