Logic gate system design

Details Logic gate system design Logic gate system design

1986-12-30

1988-12-13

Lall, Parshotam S.

Boots, shoes, and leggings

307445, 364554, 371 23, G06F 1560, G06F 1100

Patent

active

047915781

ABSTRACT:
A method for evaluating the testability of circuit systems containing a plurality of logic gates through evaluating statistical properties in response to selected inputs.

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Stefan: An Alternative to Fault Simulation, S. K. Jain, V. D. Agrawal, AT&T Bell Laboratories, Paper 2.3, IEEE 21st Design Automation Conference 1984.
Mixed-Level Fault Coverage Estimateion, H. K. Ma, A. L. Sangiovanni-Vincentelli, University of California Berkeley, Paper 32.3, IEEE 23rd Design Automation Conference 1986.

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