Logic gate having an isolation FET and noise immunity circuit

Details Logic gate having an isolation FET and noise immunity circuit Logic gate having an isolation FET and noise immunity circuit

1980-05-28

1983-11-29

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307450, 307544, H03K 19003, H03K 19017, H03K 19094, H03K 1920

Patent

active

044182910

ABSTRACT:
A field effect transistor (FET) logic gate wherein a plurality of FETs is coupled to an output enhancement mode FET through a noise immunity circuit, such noise immunity circuit including a Schottky diode. A biasing network ensures that any conducting one of the input transistors produces a forward voltage drop between its input and output less than the forward drop of the Schottky diode circuit ensuring that the voltage at the gate electrode of the output transistor is less than the threshold voltage of such output transistor in the presence of noise. In one embodiment the logic gate includes a coupling FET having a gate electrode coupled to the gate electrode of the output transistor through the noise immunity Schottky diode circuit, and a source electrode coupled to the plurality of input transistors. A first current source is coupled to the gate of the coupling transistor and thereby provides a sufficient voltage to drive the output transistor into full conduction when the input transistors are in low conduction states. A second current source is coupled to the drain electrode of the coupling transistor and supplies a predetermined amount of current to a conducting one, or ones, of such input transistors. The current supplied by the second current source is determined in accordance with the fan-out requirements of the logic gate and is independent of a bias voltage provided by the first current source at the gate electrode of the output transistor to place the output transistor into full conduction.

REFERENCES:
patent: 3969632 (1976-07-01), Bobenrieth
patent: 4013896 (1977-03-01), Picquendar
patent: 4177390 (1979-12-01), Cappon
patent: 4300064 (1981-11-01), Eden
Suzuki et al., "Logic Circuits with 2 .mu.m Gate Schottky Barrier FETs", Proc. of 6th Conf. on Solid State Devices, Tokyo, Jap., 1974; pp. 219-224.
Nuzillat et al., "A Subnanosecond Integrated Switching Circuit with MESFET's for LSI"; IEEE-JSSC; vol. SC-11, No. 3, pp. 385-394; 6/76.
Zuleeg et al., "Femtojoule High-Speed Planar GaAs E-JFET Logic"; IEEE Trans. on Electron Devices, vol. ED-25, No. 6, pp. 628-639; 6/78.
Van Tuyl et al., "GaAs MESFET Logic with 4-GHz Clock Rate"; IEEE JSSC; vol. SC-12, No. 5, pp. 485-496; 10/1977.

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