Logic gate circuit having P- and N- channel transistors coupled

Details Logic gate circuit having P- and N- channel transistors coupled Logic gate circuit having P- and N- channel transistors coupled

1984-01-31

1986-12-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307463, 307585, H03K 19096

Patent

active

046314253

ABSTRACT:
A logic circuit on a semiconductor chip having a decoding or a selecting function has at least two input transistors coupled in parallel between an output node and a reference point. Input signals are applied to the input transistors, and an output is derived from the output node. Instead of employing inverters to produce complement signals, a conductivity of one input transistor is made different from that of the other input transistors. The proposed logic circuit can decode or select a combination pattern of input signals without using a complement signal producing circuit. Therefore, the number of circuit elements and signal lines are decreased.

REFERENCES:
patent: 3651342 (1972-03-01), Dingwall
patent: 4041459 (1977-08-01), Horninger
patent: 4042915 (1977-08-01), Reed
patent: 4074151 (1978-02-01), Buckley, III et al.
patent: 4350905 (1982-09-01), Sato
patent: 4518875 (1985-05-01), Aytac

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