Logic for generating multiple clock pulses within a single clock

Details Logic for generating multiple clock pulses within a single clock Logic for generating multiple clock pulses within a single clock

1978-10-02

1980-08-12

Olms, Douglas W.

Boots, shoes, and leggings

328 38, G06F 104

Patent

active

042176395

ABSTRACT:
Clock logic for generating multiple clock pulses during a single clock cycle. In response to a signal indicative of a clock cycle, effectively two clock pulses are produced in a relatively short period of time. Such logic, which includes a delay element, causes first a load pulse to be produced thereby enabling the loading of information into, for example, a register. Additionally, and within the same clock cycle as the load pulse and in response to the same signal, an increment pulse is produced to, for example, increment a counting function which may be included in such register.

REFERENCES:
patent: 3167716 (1965-01-01), Williams et al.
patent: 3993957 (1976-11-01), Davenport
patent: 3993981 (1976-11-01), Cassarino et al.

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