Logic families interface circuit and having a CMOS latch for con

Details Logic families interface circuit and having a CMOS latch for con Logic families interface circuit and having a CMOS latch for con

1984-03-30

1985-12-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307279, H03K 19094, H03K 19092, H03K 19017, H03K 3356

Patent

active

045582378

ABSTRACT:
An interface circuit to couple logic signals from a logic gate of one kind of logic family to a logic gate of another operating at different logic state voltages, where a latch circuit is used with the first of two cascaded inverters to provide the desired interface circuit signal characteristics. One inverter is provided with a supply reduction threshold means as is another inverter in the latch so that the two inverters perform substantially similarly to one another. The latch allows independent adjustments of opposite direction logic level transitions to provide a desired noise margin.

REFERENCES:
patent: 3873856 (1975-03-01), Gerlach et al.
patent: 4075690 (1978-02-01), Oberman et al.
patent: 4258272 (1981-03-01), Huang
patent: 4406957 (1983-09-01), Atherton
patent: 4430582 (1984-02-01), Bose et al.
patent: 4469959 (1984-09-01), Luke et al.
patent: 4471242 (1984-09-01), Noufer et al.
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4501978 (1985-02-01), Gentile et al.
patent: 4504747 (1985-03-01), Smith et al.
Dingwall, "TTL-to-CMOS Buffer Circuit"; RCA Technical Notes; TN No.: 1114; 3 pp.; 6/11/1975.

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