Logic edge timing generation

Details Logic edge timing generation Logic edge timing generation

1989-07-07

1991-01-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307603, 307268, 328114, 328 55, H03K 500, H03K 513

Patent

active

049856391

ABSTRACT:
An edge generation circuit phase delays pulses of a first signal propagated on an integrated circuit. The edge generation circuit includes a first variable delay circuit located on the integrated circuit, a delay line located off the integrated circuit and a second variable delay circuit located on the integrated circuit. The first variable delay circuit receives the first signal and produces a second signal which is in phase with the first signal. The delay line receives the second signal and produces a third signal. The third signal is delayed in phase from the second by a precise amount. The second variable delay circuit receives the third signal from the delay line and produces a fourth signal. The fourth signal is in phase with the third signal.

REFERENCES:
patent: 3290590 (1966-12-01), Baker
patent: 4645947 (1987-02-01), Prak
patent: 4675546 (1987-06-01), Shaw
patent: 4703251 (1987-10-01), Baumgartner et al.
patent: 4748348 (1988-05-01), Thong
patent: 4868514 (1989-09-01), Azevedo et al.

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