Logic coincidence gate, triplet of logic gates and sequential lo

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307448, 307453, 307481, 307471, 377118, 377129, H03K 19094, H03K 19096, H03K 2117, H03K 2700

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active

047483474

ABSTRACT:
The invention pertains to programmable fast logic.
The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, linked to the drain, is joined to the drain of the first inverter which may have additional inputs (OR function). A triplet of three series-mounted logic gates comprises a programming input at the third gate, a re-looping output and, in the case of a sequence of triplets, re-looping inputs at the first gate of the first triplet. A programmable logic circuit is obtained by a sequence of series-mounted triplets which are all looped back to the first gate of the sequence. The programming is obtained by placing one or two programming inputs at the logic 0 level.
Application: Programmable frequency divider circuits in which the ratios follow one another, one by one.

REFERENCES:
patent: 3564596 (1971-02-01), Pryor, Jr.
patent: 3571727 (1971-03-01), Lombardi
patent: 3700916 (1972-10-01), Vittoz
patent: 4193037 (1980-03-01), Kyu
patent: 4587664 (1986-05-01), Iida
patent: 4639621 (1987-01-01), Ikawa et al.
Conference Proceedings of the 11th European Microwave Conference, Sep. 7-11, 1981, RAI International Congress Centre, Amsterdam, Netherlands; pp. 28-37; G. Nuzillat: "GaAs Digital ICs for High-Speed Signal Processing".
IEEE Transactions on Electronic Devices, vol. ED-27, No. 6, Jun. 1980, pp. 1102-1109, IEEE, New York, U.S.; G. Nuzillat et al; "Quasi-Normally-Off MESFET Logic for High-Performance GaAs IC's".

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