Logic circuits with data resynchronization

Details Logic circuits with data resynchronization Logic circuits with data resynchronization

1989-05-26

1990-04-17

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072722, 307480, H03K 515, H03K 19003

Patent

active

049183311

ABSTRACT:
In relatively large systems of (integrated) circuits, data signals can experience a delay which is in the order of magnitude of a clock-pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses are led via a delaying element (for example, the inverting circuits in series) to the receiving circuit (slave of the master/slave flip-flop). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/slave flip-flop), which receives the undelayed clock pulses, the data delay between the receiving circuit and the other circuit being negligible. The data delay is thus distributed over two clock pulses.

REFERENCES:
patent: 4540903 (1985-09-01), Cooke et al.

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