Logic circuits and on-chip four phase FET clock generator made t

Details Logic circuits and on-chip four phase FET clock generator made t Logic circuits and on-chip four phase FET clock generator made t

1975-08-25

1977-07-05

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307208, 307265, H03K 513, H03K 3353, H03K 1908, H03K 1920

Patent

active

040342425

ABSTRACT:
A phased, four-output clock generator implemented on-chip with MOSFETs, has two phased inputs .phi..sub.A and .phi..sub.B thereto. If .phi..sub.A and .phi..sub.B are properly time-phased (in sequence: .phi..sub.A =1, .phi..sub.B =0; .phi..sub.A =0, .phi..sub.B =0; .phi..sub.A =0, .phi..sub.B =1; and .phi..sub.A =0, .phi..sub.B =0) the four outputs are time phased as:

REFERENCES:
patent: 3365707 (1968-01-01), Mayhew
patent: 3395291 (1968-07-01), Bogert
patent: 3536936 (1970-10-01), Rubinstein et al.
patent: 3564299 (1971-02-01), Varadi
patent: 3596108 (1971-07-01), Heeren
patent: 3641370 (1972-02-01), Heimbigner
patent: 3659286 (1972-04-01), Perkins et al.
patent: 3740660 (1973-06-01), Davies, Jr.
Chin et al., "Gated Inverter Using Complementary Metal-Oxide-Silicon Transistors;" vol. 16, No. 7, pp. 2289-2290; Dec. 1973.

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