Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1998-05-18
2001-06-19
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S225000
Reexamination Certificate
active
06249163
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital electronic circuits and in particular to transparent latches.
2. Discussion of Prior Art
A transparent latch is a digital function which has one signal input (D), one signal output (Q) and a control input C.
The control input is used to select one of two modes of operation. In a first mode, the output (Q) changes to follow any changes in the input (D). In the second mode, the output remains set to the input condition existing at the point of mode change.
The above function can be represented by either of the following Boolean expression:
Q=D.C+Q.{overscore (C)}
when the first mode is such that C is true: or by its dual:
Q=D.{overscore (C)}+Q.C
when the first mode is such that C is false
The above expressions can be realised in a number of known ways, one of which is shown in FIG.
1
. The transparent latch of FIG.
1
and other known versions are described in Texas instruments Data Book Vol I 1989.
The truth table (where H=true and L=false) for the circuit of
FIG. 1
is as below:
D
C
Q
H
H
H
L
H
L
H
L
Q
0
L
L
Q
0
i.e. when the control input (C) is high, the latch is transparent, with Q following D, and when the control input (C) is low the output Q remains latched at its previous level Q
o
.
The circuit of
FIG. 1
comprises first and second AND gates
1
,
2
whose outputs are fed to an OR gate
3
which provides the final output Q. Inputs D and C are fed to the first AND gate
1
while the second AND gate
2
receives the final output Q and {overscore (C)} as inputs. {overscore (C)} is derived from C by means of an inverter/NOT gate
4
.
As can readily be seen from inspection of
FIG. 1
, the OR gate
3
makes the choice between D or the existing value of Q, the choice being controlled by the current state of C, this being the principle of operation of all known transparent latches.
It will also be noted that for correct operation of the circuit under all possible conditions, particular care must be taken in the layout of the latch so that propagation delays through gates and interconnecting wires and are accounted for. This constraint on the design layout is inherent in all known latches. If these propagation delays are not properly accounted for then a failure condition can occur. For example, when the control input (C) is high and D is high, the input to gate
3
from gate
1
will be high and the input to gate
3
from gate
2
will be low. If the control input (C) is now taken low and the input to gate
3
from gate
1
goes low before the input to gate
3
from gate
2
goes high, the output (Q) can be erroneously latched low.
SUMMARY OF THE INVENTION
An object of this invention is to provide a transparent latch design in which the above constraint is removed.
Accordingly, this invention comprises a transparent latch having a signal input, D, an operating mode control input, C, and an output, Q, and including logic gate means for allowing the output signal level to follow the input signal level in a first operating mode, and for blocking any level change in the input signal from propagating through to the output in a second operating mode. A transparent latch in accordance with the invention will always latch the correct value no matter what combination of propagation delays through gates or wires (or switching speed of gates) exist in the physical realisation.
In contrast with known transparent latches, the present invention does not use a control signal C and its inverse {overscore (C)}, but just one control, C. Owing to the design of the latch of the present invention, relative propagation delays through gates and interconnecting wires do not affect the value latched, therefore there are no constraints on its physical layout.
Also in contrast with known devices which latch by selecting the existing output level, the latch of the present invention stays latched by blocking any subsequent changes in signal input level.
In a specific embodiment, the latch consists of two pairs of logic gates in which the output of each gate comprising a pair is fed back to the input of the other gate comprising the same pair. The control input, C, is applied to both pairs, with the signal input, D, being applied just to a first pair. The output of the first pair is then connected to an input of the second.
REFERENCES:
patent: 4002933 (1977-01-01), Leuschner
patent: 4156154 (1979-05-01), Iizuka
patent: 5004933 (1991-04-01), Widener
patent: 5781053 (1998-07-01), Ramirez
patent: 38 1313816 A1 (1989-11-01), None
patent: 1-13808 (1989-01-01), None
“A Scan Design for Asynchronous Sequential Logic Circuits Using SR-Latches”, Shieh, Ming-Der et al, pp. 1300-1303, Proceedings of the Midwest Symposium on Circuits and Systems, Detroit, Aug. 16, 1993, vol. 2, Institute of Electrical and Electronics Engineers.
Lam Tuan T.
Matra BAe Dynamics (UK) Limited
Nixon & Vanderhye P.C.
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