Logic circuitry for selection of dedicated registers

Details Logic circuitry for selection of dedicated registers Logic circuitry for selection of dedicated registers

1975-02-18

1977-02-01

Yusko, Donald J.

Communications: electrical

Digital comparator systems

178 50, 178 58R, 179 15A, 340173R, H04Q 900, G11C 1700, H04L 500

Patent

active

040064573

ABSTRACT:
An MOS (Metal-Oxide-Semiconductor) integrated circuit includes four dedicated registers thereon, two of which are "write only" registers having the capability of being written into, but not read from, by means of buffer circuitry for coupling a bidirectional data bus to the dedicated registers. The other two dedicated registers are "read only" registers having the capability of being read from, but not written into, by means of the buffer circuitry. The integrated circuit chip is itself addressable by means of a plurality of address conductors of an address bus coupleable to the integrated circuit chip, and the four dedicated registers within the integrated circuit chip are further addressable by means of an additional address conductor called a register select address line. A control input conductor is coupled to the integrated circuit chip and is used to control the direction of data flow of the buffer circuitry and is also used in conjunction with the register select address line to select one of four dedicated registers. This provides the advantage of reducing the number of external connections required for the integrated circuit chip, and is possible only because the registers are dedicated.

REFERENCES:
patent: 3781826 (1973-12-01), Beausoleil
patent: 3832688 (1974-08-01), Strojny et al.
patent: 3882470 (1975-05-01), Hunter
patent: 3892925 (1975-07-01), Fisk et al.
patent: 3900833 (1975-08-01), Rogers
patent: 3942162 (1976-03-01), Buchanan

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