Logic circuit with additional circuit for carrying out delay tes

Details Logic circuit with additional circuit for carrying out delay tes Logic circuit with additional circuit for carrying out delay tes

1991-09-06

1994-07-12

Beausoliel, Jr., Robert W.

Excavating

H04B 1700

Patent

active

053295323

ABSTRACT:
The first and second flip-flop circuits are connected in series included within a combinational logic for carrying out a delay test. The first and second flip-flop circuits are provided with control pins, system clock pins, scan clock pins, system data pins and scan data pins, respectively. A delay time propagated from the first flip-flop circuit to the second flip-flop circuit through the path of the combinational logic to be tested is measured by detecting an input time to the first flip-flop circuit by the system clock signal to the first flip-flop circuit in response to an input signal to the control pins and a time stored in the second flip-flop circuit corresponding to output system data from the first flip-flop circuit. By measuring the delay time, whether the combinational logic is normal or abnormal is detected.

REFERENCES:
patent: 4669061 (1987-05-01), Bhavsar
patent: 4894830 (1990-01-01), Kawai
patent: 5006787 (1991-04-01), Katircioglu et al.
patent: 5027355 (1991-06-01), Stoica
patent: 5103167 (1992-04-01), Okano et al.

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