Logic circuit verification device to verify the logic circuit eq

Details Logic circuit verification device to verify the logic circuit eq Logic circuit verification device to verify the logic circuit eq

1997-08-14

1999-09-07

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

059496916

ABSTRACT:
A logic circuit verification device comprising a data input section to read the circuit data and the circuit information of the logic circuits to be verified and converts them into the intermediate format, a corresponding point detection section to extract and output the information about the corresponding points using the corresponding point detection algorithm, a circuit partitioning section to read the intermediate format data and partition the logic circuits according to the corresponding point information obtained by the corresponding point detection section so as to prepare circuit data of the subcircuits and a equivalence checking section to read the circuit data of the subcircuits, determine the subcircuits to be compared with referring to the corresponding point information obtained by the corresponding point detection section and comparatively compares the circuit data of the subcircuits.

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Wolfgang Kunz et al., "A Novel Framework for Logic Verification in a Synthesis Environment", IEEE Transactions on Computer-Aided Design of Intergrat ed Circuits and Systems, vol. 15 No. 1, Jan. (1996), pp. 1-7.
A. Mukaiyama et al., "Logic Verification System: Condor", NEC Corporation, Jul. (1992), pp. 17-22.

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