Logic circuit used in standard IC or CMOS logic level

Details Logic circuit used in standard IC or CMOS logic level Logic circuit used in standard IC or CMOS logic level

1988-02-09

1990-02-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307452, 307570, 307571, H03K 1902, H03K 19092, H03K 19096

Patent

active

049029142

ABSTRACT:
A logic circuit includes first and second NPN bipolar transistors whose collector-emitter paths are serially connected between a power source potential terminal and a ground terminal, the connection node of the first and second bipolar transistors being connected to a signal input terminal; a first CMOS logic circuit having an input terminal connected to a signal input terminal and an output terminal connected to the base of the first NPN bipolar transistor; a second CMOS logic circuit having an input terminal connected to the signal input terminal and an output terminal connected to the signal output terminal; a first switching circuit connected between the signal output terminal and the base of the second bipolar transistor, and to be set OFF when an input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive; and a second switching circuit connected between the second potential supply source and the base of the second NPN bipolar transistor, and to be set OFF when the input signal is set at a level at which the first NPN bipolar transistor is rendered conductive, and to be set ON when the input signal is set at a level at which the first NPN bipolar transistor is rendered nonconductive.

REFERENCES:
patent: 4616146 (1986-10-01), Lee et al.
patent: 4638186 (1987-01-01), McLaughlin
patent: 4678940 (1987-07-01), Vasseghi et al.
patent: 4694202 (1987-09-01), Iwamura et al.
Patent Abstracts of Japan, vol. 9, No. 69 (E-305)[1792], Mar. 29, 1985; & JP--A--59 205 828 (Nippon Denki K.K.) 21-11-1984.
Wakeman, "High--Speed--CMOS--Designs Address Noise and I/O Levels," EDN Electrical Design News, vol. 29, No. 8, pp. 285-290, 294, 296, Apr. 1984.

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