Logic circuit testing apparatus

Details Logic circuit testing apparatus Logic circuit testing apparatus

1987-05-28

1991-10-29

Baker, Stephen M.

Excavating

G01R 3128

Patent

active

050621106

ABSTRACT:
An improved apparatus for testing logic circuits by implementing scan-in/scan-out operations. The improved testing apparatus is provided with input terminals for receiving control signals and data signals, one or more shift-paths each of which is made up of shift registers and control means for enabling a bidirectional shift operation of the shift-paths and for controlling the directions in which the respective shift-paths shift logical values stored in the shift registers thereof. The control means sets the shift direction in accordance with the control signals provided from the input terminals. Thereby, if there is a failing shift register in a shift-path, the failing shift register can be located by implementing the scan-in/scan-out operation utilizing the bidirectional shift of the logical data in the shift-path.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 4597042 (1986-06-01), D'Angeac et al.
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4683569 (1987-07-01), Rubin
patent: 4701917 (1987-10-01), Jones et al.
Electronics, Frechette et al., "Support Processor Analyses Errors Caught by Latches", Nov. 8, 1979, pp. 116-118.
Millman, J. et al., Microelectronics, 2nd ed., 1987, pp. 327-329.

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