Logic circuit system with latch circuits for reliable scan-path

Details Logic circuit system with latch circuits for reliable scan-path Logic circuit system with latch circuits for reliable scan-path

1988-04-21

1990-07-17

Fleming, Michael R.

Excavating

371 251, G01R 3128

Patent

active

049425773

ABSTRACT:
An IC logic circuit includes a combinational network of a plurality of logic circuits, a plurality of latches having a D-type flip-flop and a delay circuit, the output from the D-type flip-flop being directly applied to one of the logic circuits and indirectly derived through the delay circuit, a plurality of selectors disposed between two latches to selectively applying an output from the logic circuit or an output from the preceding stage latch to the succeeding stage latch, and a means for supplying clock signal to said D-type flip-flops, a delay time of the delay circuit being longer than a time period spending in the clock signal supplying means.

REFERENCES:
patent: 4602349 (1986-07-01), Blackley
patent: 4701920 (1987-10-01), Resnick
patent: 4710931 (1987-12-01), Bellay
patent: 4825439 (1989-04-01), Sakashita

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