Logic circuit simulator for verifying circuit operations having

Details Logic circuit simulator for verifying circuit operations having Logic circuit simulator for verifying circuit operations having

1992-10-08

1994-09-06

Harvey, Jack B.

Boots, shoes, and leggings

364488, 364489, 364490, 364491, 371 23, G06F 1560

Patent

active

053454014

ABSTRACT:
A MOST output signal determiner (4) with output signal strength verifying function receives a circuit connection data (D4) with MOS input information to determine the signal strength of an output signal which appears at an output terminal (drain or source) of an MOS transistor as a function of an input signal. A logic simulator verifies circuit operating characteristics in consideration for signal transmitting characteristics on the input signal of the MOST, the presence/absence of a through current in the MOST and an accurate state transition delay time through the MOST.

REFERENCES:
patent: 5016204 (1991-05-01), Simoudis et al.
patent: 5051911 (1991-09-01), Kimura et al.
patent: 5202841 (1993-04-01), Tani
patent: 5293327 (1994-03-01), Ikeda et al.
Principles of CMOS VLSI Design, Oct. 1985, N. Weste, et al., Chapter 2.2 pp. 39-43, "MOS Device Design Equations", Chapter 2.5, pp. 55-57, Transmission Gate-DC Characteristics, Chapter 4.3, pp. 122-130, Capacitance Estimation.

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