Logic circuit simulation apparatus having cycle-based simulator

Details Logic circuit simulation apparatus having cycle-based simulator Logic circuit simulation apparatus having cycle-based simulator

1998-01-21

2000-06-13

Teska, Kevin J.

39550035, 39550007, 39550034, G06F 9455

Patent

active

060759364

ABSTRACT:
Where the output delay of a combinational circuit in a logic circuit is defined by a clock cycle count, data transfer means for outputting data delayed in the same number of clock cycles is inserted in a block of a cycle-based simulator. The data transfer means comprises registers or a combination of registers and selectors. The cycle-based simulator may be further arranged to automatically recognize the output delay of a combinational circuit in a target logic circuit. Data transfer means for effecting an output delay in the recognized number of clock cycles is then automatically inserted in a block of the cycle-based simulator.

REFERENCES:
patent: 5630100 (1997-05-01), Ganapathy et al.
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 5696942 (1997-12-01), Palnitkar et al.
patent: 5790836 (1998-08-01), Mizumo
Khoo, Kei-Yon; Willson, A. N., Jr.;"Cycle-based Timing Simulations Using Event-Streams", Prodeedings of the IEEE Interantional Conference on Computer Design: VLSI in Computers and Processors, pp. 460-465, Oct. 1996.

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