Logic circuit optimization apparatus and its method

Details Logic circuit optimization apparatus and its method Logic circuit optimization apparatus and its method

1997-01-29

1999-03-16

Trans, Vincent N.

Boots, shoes, and leggings

364578, G06F 1750

Patent

active

058838082

ABSTRACT:
An optimization apparatus comprises a hierarchical circuit specification input for entering a logic circuit having a hierarchical structure, a delay constraint input for entering delay constraints of the logic circuit, a circuit database for storing and holding the logic circuit and delay constraint, a timing analyzer for performing the timing analysis of the logic circuit, a delay constraint distributor for distributing the delay constraints to each hierarchical configuring the logic circuit according to optimization possibility of the logic circuit, an optimizing unit for performing the delay optimization of the logic circuit according to the delay constraints distributed to the respective hierarchical sub-circuit of the logic circuit, a library input for entering library information to be used for the timing analysis of the logic circuit, a library database for holding the library information, and an output for outputting the optimized logic circuit.

REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5210700 (1993-05-01), Tom
patent: 5353433 (1994-10-01), Sherman
patent: 5365463 (1994-11-01), Donath et al.
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5475607 (1995-12-01), Apte et al.
patent: 5508937 (1996-04-01), Abato et al.
patent: 5544071 (1996-08-01), Keren et al.
patent: 5563800 (1996-10-01), Matsumoto et al.
patent: 5581738 (1996-12-01), Dombrowski
patent: 5636372 (1997-06-01), Hathaway et al.
patent: 5726902 (1998-03-01), Mahmood et al.
patent: 5778216 (1998-07-01), Venkatesh
patent: 5790435 (1998-08-01), Lewis et al.
patent: 5790830 (1998-08-01), Segal
Gutwin et al., "Delay Prediction for Technology-Independent Logic Equations", pp. 1-10.

Affiliated with

Also associated with

Rating

Logic circuit optimization apparatus and its method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic circuit optimization apparatus and its method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit optimization apparatus and its method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-822903