Logic circuit of ratioless structure

Details Logic circuit of ratioless structure Logic circuit of ratioless structure

1976-06-22

1977-10-11

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, H03K 1908

Patent

active

040537919

ABSTRACT:
A logic circuit of a ratioless structure, wherein a load MOS FET, a drive MOS FET and a pre-discharge MOS FET are connected in series in the described order, a first clock is applied to the pre-discharge MOS FET, a second clock is applied to the load MOS FET, and an input signal is applied to the drive MOS FET while an output signal is derived from the junction between the drive MOS FET and pre-discharge MOS FET.

REFERENCES:
patent: 3497715 (1970-02-01), Yen
patent: 3524077 (1970-08-01), Kaufman
patent: 3617767 (1971-11-01), Booher
patent: 3676709 (1972-07-01), Ducamus et al.
Terman -- IBM Tech. Disclosure Bul., vol. 12, No. 3, Aug. 1969, "Three-Phase Shift Register".

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