Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-09-22
2010-10-26
Silver, David (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000
Reexamination Certificate
active
07822591
ABSTRACT:
A logic circuit model conversion apparatus includes a first analysis unit which analyzes a model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks and an analysis result, a creating unit which creates a common execution frequency group that is a set of codes whose execution frequency becomes common, based on the simultaneous blocks and analysis result, a second analysis unit which analyzes the common execution frequency group and creates a formula of a general term to derive a predetermined value of each register, a third analysis unit which analyzes a mutual relationship between the common execution frequency groups and derives an execution frequency of each common execution frequency group up to a predetermined time, and a deriving unit which derives a value of each of the registers at the predetermined time from the formula of the general term and execution frequency.
REFERENCES:
patent: 5577233 (1996-11-01), Goettelmann et al.
patent: 5862361 (1999-01-01), Jain
patent: 5995736 (1999-11-01), Aleksic et al.
patent: 6263495 (2001-07-01), Kataoka
patent: 6295627 (2001-09-01), Gowni et al.
patent: 6438730 (2002-08-01), Atmakuri et al.
patent: 7024652 (2006-04-01), McGaughy et al.
patent: 2002/0032894 (2002-03-01), Miyazaki et al.
patent: 2005/0044438 (2005-02-01), Nonogaki et al.
patent: 2005/0268268 (2005-12-01), Wang et al.
patent: 2005-62106 (2005-03-01), None
Andy Zaidman, Serge Demeyer, “Managing Trace Data Volume through a Heuristical Clustering Process Based on Event Execution Frequency,” Software Maintenance and Reengineering, European Conference on, pp. 329, Eighth Euromicro Working Conference on Software Maintenance and Reengineering (CSMR'04), 2004.
Nonogaki Nobuhiro
Otsuki Tomoshi
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Shah Kamini S
Silver David
LandOfFree
Logic circuit model conversion apparatus and method thereof;... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic circuit model conversion apparatus and method thereof;..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit model conversion apparatus and method thereof;... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4192826