Logic-circuit layout pattern inspection method and logical simul

Details Logic-circuit layout pattern inspection method and logical simul Logic-circuit layout pattern inspection method and logical simul

1992-08-27

1995-01-10

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364578, G06F 1560

Patent

active

053813456

ABSTRACT:
A circuit layout pattern inspection method and a logical simulator for implementing the same. Wiring is substituted by a .pi. or T equivalent circuit and is described by a nodal equation, and a gate is described by a simplified model, that is, a current source calculation formula. By the nodal equation and the current source calculation formula, a simulation is performed to obtain a delay time for every node. The obtained delay time is stored to make the inspection easy.

REFERENCES:
patent: 4823278 (1989-04-01), Kikuchi et al.
patent: 5031111 (1991-07-01), Chao et al.
patent: 5046017 (1991-09-01), Yuyama et al.
patent: 5197015 (1993-03-01), Hartoog et al.

Affiliated with

Also associated with

Rating

Logic-circuit layout pattern inspection method and logical simul does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic-circuit layout pattern inspection method and logical simul, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic-circuit layout pattern inspection method and logical simul will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-855549