Logic circuit having individually testable logic modules

Details Logic circuit having individually testable logic modules Logic circuit having individually testable logic modules

1987-06-02

1989-08-22

Smith, Jerry

Excavating

G01R 3128

Patent

active

048602906

ABSTRACT:
A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes. An additional SRL is contained within each test port, and in the scan path, for storing a logic state corresponding to whether the functional circuitry in the module is to be connected to or disconnected from the system bus during the test sequence. A configuration if further disclosed which has global SRLs in the modules; such global SRLs are always in the scan path, regardless of whether or not the module containing them is selected. Multiplexing of the scan data and the configuration data is also disclosed.

REFERENCES:
patent: 4597042 (1986-06-01), d'Angeac
patent: 4698588 (1987-10-01), Huang
patent: 4701921 (1987-10-01), Powell
patent: 4710931 (1987-12-01), Bellay
patent: 4710933 (1987-12-01), Powell
E. J. McCluskey, "A Survey of Design for Testability Scan Techniques", VLSI Design, 12/1984 pp. 38-61.

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