Logic circuit having carry select adders

Details Logic circuit having carry select adders Logic circuit having carry select adders

1991-02-22

1991-09-10

Clark, David L.

Boots, shoes, and leggings

G06F 750

Patent

active

050479768

ABSTRACT:
An operation circuit for M-bits parallel full addition includes partitioned adders and first and second multiplexers. Each of the first multiplexers selects one of paired provisional carry signals C.sub.ns-1 (1) and C.sub.ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C.sub.(s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C.sub.ns-1 to be progatatd from the s-th partitioned adder. Each of the second multiplexers generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k=n(s+1)-1, n(s+2) -1, . . . , n(s+l)-1) by referring to paired provisional carry signals Cr(1) (or Cr*(1); r=k-n=ns-1) and Cr(0) (or Cr*(0); k-n=ns-1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate l real carry signals Ck at the same time by selecting either the provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C.sub.(s-1)n-1 relating to a digit which is one digit lower than the lowest-order digit of the s-th partitioned adder.

REFERENCES:
patent: 4675838 (1987-06-01), Mazin et al.
E. C. Dunn et al., "Arithmetic Unit Using Table Look-Up", IBM Technical Disclosure Bulletin, vol. 12, No. 11, Apr. 1970, pp. 1800-1801.
R. B. Anderson, "Five-Level Combinations Sum Predict & Carry Propagate Adder", IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, pp. 112-113.

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