Logic circuit having an output signal with a gentle leading edge

Details Logic circuit having an output signal with a gentle leading edge Logic circuit having an output signal with a gentle leading edge

1988-03-25

1989-10-31

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307263, 307363, 307555, H03K 1716

Patent

active

048779750

ABSTRACT:
To obtain a logic result output signal with a gentle leading edge at high response speed, the logic circuit comprises an input section for receiving at least one input signal to find a logic result signal; a control section including at least one first transistor, having a constant collector load connected between the collector thereof and a supply voltage, turned on or off in response to the logic result signal to generate a control signal; an output section including at least two second and third transistors turned on or off alternatively in response to the control signal to generate a logic output signal; and a variable resistance circuit connected in parallel to the constant collector load, for increasing the resistance of the collector load (i.e. time constant at the collector) with increasing collector potential of the first transistor. The variable resistance circuit includes diodes connected in series or a transistor. The leading edge of the logic output signal rises sharply in accordance with a small time constant (i.e. low collector resistance) and thereafter gently in accordance with a large time constant (i.e. high collector resistance).

REFERENCES:
patent: 4409498 (1983-10-01), Dorler et al.
patent: 4567378 (1986-01-01), Raver
patent: 4605870 (1986-08-01), Dansky et al.
patent: 4622482 (1986-11-01), Ganger
patent: 4737665 (1988-04-01), Ovens
patent: 4746817 (1988-05-01), Banker et al.

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