Logic circuit for reliability and yield enhancement

Details Logic circuit for reliability and yield enhancement Logic circuit for reliability and yield enhancement

1990-10-01

1993-03-30

Beausoliel, Jr., Robert W.

Excavating

371 501, 371 3, 371 225, 365200, G06F 1540, G06F 1100

Patent

active

051990350

ABSTRACT:
A logic circuit for testing the reliability of an ASIC includes an array circuit having a plurality of matrix arrays each having a plurality of inputs. The plurality of matrix arrays being positioned in a predetermined row and column of the array circuit and being responsive to a plurality of input signals applied thereto for providing a respective row and column output. A parity circuit responsive to the row and column outputs of the plurality of matrix arrays for causing an output signal at an output of the logic circuit to be in a first logic state whenever the row outputs of the plurality of matrix arrays are logically different, or whenever the column outputs of the plurality of matrix arrays are logically different. A stimulus circuit coupled to the plurality of inputs of the plurality of matrix arrays for supplying the plurality of input signals to exhaustively stimulate each one of the plurality of matrix arrays with all possible logic combinations. A verification circuit for verifying the operation of the parity circuit by stimulating the parity circuit with a predetermined logic sequence. The reliability and functionality of the ASIC can be determined by observing a frequency of the output signal supplied at the output of the logic circuit wherein the frequency of the output signal is a function of the number of defects occurring within the array circuit and the parity circuit.

REFERENCES:
patent: 3958110 (1976-05-01), Hong
patent: 4464747 (1984-08-01), Groudan
patent: 4541090 (1985-09-01), Shiragasawa
patent: 4878220 (1989-10-01), Hashimoto
patent: 5075892 (1991-12-01), Choy
patent: 5083083 (1992-01-01), El-Ayat

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