Logic circuit employing field effect transistor having junction

Details Logic circuit employing field effect transistor having junction Logic circuit employing field effect transistor having junction

1988-03-02

1990-02-13

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307464, 307471, H03K 19094, H03K 1921

Patent

active

049009532

ABSTRACT:
A logic circuit comprises a first terminal for receiving a first power source voltage, a second terminal for receiving a second power source voltage lower than the first power source voltage, a third terminal for receiving a reference voltage, an input terminal for receiving an input voltage, an output terminal for outputting an output voltage, a load coupled between the first terminal and the output terminal, and first and second field effect transistors (FETs) coupled in series between the output terminal and the second terminal. The first FET is coupled to the output terminal and has a gate coupled to the third terminal. The second FET is coupled to the second terminal. The second FET has a gate coupled to the input terminal, and has a junction with a rectifying characteristic between the gate and source thereof.

REFERENCES:
patent: 4048518 (1977-09-01), Koo
patent: 4518871 (1985-05-01), Toyoda et al.
patent: 4743782 (1988-05-01), Nelson et al.
patent: 4755695 (1988-07-01), Suzuki
"Resonant-Tunneling Hot Electron Transistors (RHET): Potential and Applications", Naoki Yokoyama, the 18th (1986 International) Conference on Solid State Devices and Materials, Aug. 20-22, 1986, pp. 347-350.

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