Logic circuit delay stage and delay line utilizing same

Details Logic circuit delay stage and delay line utilizing same Logic circuit delay stage and delay line utilizing same

1998-07-06

2000-10-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327149, 327161, H03H 1126

Patent

active

061373346

ABSTRACT:
The present invention is embodied in a method and apparatus for improving a delay line circuit of a Digital Delay Lock Loop (DDLL) circuit. Each delay stage of the delay line consists of three gates, two NANDs and one inverter. The reduction in the total number of gates decreases the unit delay time for each stage, improving the resolution of each stage of the delay line. In addition, the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line, resulting in an overall decrease in the size of the DDLL circuit.

REFERENCES:
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patent: 5663665 (1997-09-01), Wang et al.
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5717353 (1998-02-01), Fujimoto
patent: 5744991 (1998-04-01), Jefferson et al.
patent: 5946268 (1999-08-01), Iwamoto et al.
Hatakeyama et al., "A 256-Mb SDRAM Using a Register-Controlled Digital DLL," IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1728-1732.
Eto et al., "A 1Gb SDRAM with Ground Level Precharged Bitline and Non-Boosted 2.1V Word Line," ISSCC Digest of Technical Papers, pp. 82-83, Feb. 1998.

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