Logic circuit building block and systems constructed from same

Details Logic circuit building block and systems constructed from same Logic circuit building block and systems constructed from same

1984-01-20

1985-05-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307440, 328205, 377 54, 377119, H03K 2304

Patent

active

045174741

ABSTRACT:
A logic system which includes a plurality of identical logic circuit building blocks, each referred to as an M Circuit, is disclosed. The M Circuits are connected in a linear array of interconnected M Circuits including first through last M Circuits, the linear array providing a latch operation. The system comprises a plurality of M Circuits each of which responds to transitions of a two-level binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B. Each of the M Circuits comprises a gate having two inputs connected to the A and B input terminals, resepectively, and a set-reset flip flop having its set input connected to the output of the gate, the reset input connected to the B input terminal and the set and reset outputs connected, respectively, to the output terminals Q and Q of the M Circuit. The Q and Q output terminals provide complementary binary outputs for any combination of binary inputs applied at the A and B input terminals, whereby the M Circuit is a four terminal device which responds to each transition of the input signal at the A and B terminals to provide outputs at the Q and Q terminals in accordance with the truth table function. One of the output terminals of each of the first through next to last M Circuits are connected to the B input terminal of the succeeding M Circuit. The A input terminals of the M Circuits are coupled together, the A input terminals being coupled to a source of an input signal. One of the output terminals of the last M Circuit is connected as a reset line to the B input terminal of the first M Circuit, whereby one of the output terminals of the first M Circuit may be provided as a latch output line for operating an output device in response to the input signal.

REFERENCES:
patent: 3778794 (1973-12-01), Szabo et al.

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