Logic circuit arrangements using insulated-gate field effect tra

Details Logic circuit arrangements using insulated-gate field effect tra Logic circuit arrangements using insulated-gate field effect tra

1976-03-18

1976-11-02

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307214, 307215, 307218, 307279, H03K 1908, H03K 1920, H03K 1934, H03K 1936

Patent

active

039899551

ABSTRACT:
A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting.

REFERENCES:
patent: 3573487 (1971-04-01), Polkinghorn
patent: 3573498 (1971-04-01), Ahrons
patent: 3573507 (1971-04-01), Eng
patent: 3588527 (1971-06-01), Cricchi
patent: 3641511 (1972-02-01), Cricchi et al.
patent: 3714466 (1973-01-01), Spence
patent: 3720841 (1973-03-01), Suzuki
patent: 3739193 (1973-06-01), Pryor
patent: 3745371 (1973-07-01), Suzuki
patent: 3766408 (1973-10-01), Suzuki et al.
reynolds et al., "Metal-Oxide-Semiconductor(MOS) Integrated Circuits"; Post. Off. Elect. Engrs. J.(G.B.); vol. 63, pt. 2 (7/1970); pp. 105-112.
Saffir, "Getting More Speed From MOS"; Electronics (pub.); 2/17/69; pp. 106-109.
Lohman, "Applications of MOSFETs in Microelectronics"; SCP and Solid State Technology (pub.); 3/1966; pp. 23-29.

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